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==Timings and Contention==
 
==Timings and Contention==
The contention and ram timings on the +3 and Black +2 differ significantly from earlier models due to the redesigned [[The Amstrad ASIC|gate array]]. Timing patterns and memory contention are described in detail in the [[Contended memory#Black +2 (+2A/B) and +3|contended memory]] article.
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The contention and ram timings on the +3 and Black +2 differ significantly from earlier models due to the redesigned [[The Amstrad gate array|gate array]]. Timing patterns and memory contention are described in detail in the [[Contended memory#Black +2 (+2A/B) and +3|contended memory]] article.