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== Memory ==
 
== Memory ==
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The SE combines the RAM paging systems of the [[Timex TS2068]] with the ZX Spectrum 128 and then adds another 16K to that. This means it uses two different systems to access its full 272K of RAM. Jarek installed his 128 compatibility upgrade to take the RAM to 144K and then installed a 128K SRAM connected to the Timex memory management unit.
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The SE combines the RAM paging systems of the [[Timex 2000 series|Timex TS2068]] with the ZX Spectrum 128 and then adds another 16K to that. This means it uses two different systems to access its full 272K of RAM. Jarek installed his 128 compatibility upgrade to take the RAM to 144K and then installed a 128K SRAM connected to the Timex memory management unit.
    
The Timex Horizontal MMU sees the RAM as three banks of memory; HOME, DOCK, and EX banks.
 
The Timex Horizontal MMU sees the RAM as three banks of memory; HOME, DOCK, and EX banks.
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Memory is paged in 8K banks from either the DOCK or the EX bank, but these banks are mutually exclusive - you cannot page in a bank from both simultaneously. Bit 7 of port 0xff determines which bank to use (0=DOCK, 1=EX-ROM). Port 0xf4 determines which banks are to be paged in with each bit referring to the relevant bank (0-7 or 0'-7'). When memory is being paged, interrupts should be disabled and the stack should be in an area which is not going to change.
 
Memory is paged in 8K banks from either the DOCK or the EX bank, but these banks are mutually exclusive - you cannot page in a bank from both simultaneously. Bit 7 of port 0xff determines which bank to use (0=DOCK, 1=EX-ROM). Port 0xf4 determines which banks are to be paged in with each bit referring to the relevant bank (0-7 or 0'-7'). When memory is being paged, interrupts should be disabled and the stack should be in an area which is not going to change.
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On a [[Timex TC2048|TC2048]], BASIC is contained in the 16K ROM area and banks 0-7 and 0'-7' are not normally available, while on a TS2068 part of the BASIC is stored in an 8K ROM in bank 0' and cartridges plugged into the dock use banks 0-7. On the SE each of these banks is connected to 64K of RAM, providing an additional 128K in addition to the base RAM.
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On a [[Timex 2000 series|TC2048]], BASIC is contained in the 16K ROM area and banks 0-7 and 0'-7' are not normally available, while on a TS2068 part of the BASIC is stored in an 8K ROM in bank 0' and cartridges plugged into the dock use banks 0-7. On the SE each of these banks is connected to 64K of RAM, providing an additional 128K in addition to the base RAM.
    
The contended memory timings for the SE are unknown but should be similar to that for the 48K machine, except that the pattern starts at a different number of T-states after the interrupt, than the usual 14335. Odd banks in the 128 scheme are contended.
 
The contended memory timings for the SE are unknown but should be similar to that for the 48K machine, except that the pattern starts at a different number of T-states after the interrupt, than the usual 14335. Odd banks in the 128 scheme are contended.