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The !CK signal, sometimes referred to as PHICPU is available on Lower Pin 8. This clock signal is generated by the ULA and is interrupted during [[contended memory]] access. This clock signal is inverted by a transistor switch to provide a clean clock edge for the Z80.
====IO Request Signals====
The !IORQ signal generated by the Z80 is connected to the !IOREQ input of the ULA via a series resistor allowing the !IOREQ pin to be pulled high by TR6 when the A0 address line is high. This has the effect of allowing the ULA to respond to an IO request only when A0 is low.
This combined !IORQ+A0 signal is connected to Lower Pin 13 and is referred to as !IORQULA or sometimes !IORQGE.
* Lower Pin 15 provides the same composite video signal that is fed into the UHF modulator.
* Lower pin 16 carries an inverted luminosity signal to use with the 'U' and 'V' colour difference signals provided on lower pins 18 and 17 respectively