Various spectrum models and peripherals use memory paging (or memory mapping) technic to extend the 64kb memory limit of Z80 CPU.
The Z80 CPU has 16 address lines and no builtin MMU unit, so it can address maximum 64KB (2^16) memory (or I/O) space (0x0000 - 0xffff).
The original ZX Spectrum 16K/48K (or the ZX Spectrum+) only uses maximum 64KB memory (16KB ROM and 16KB or 48KB RAM), but other models (128K) and several peripheral have extra RAM or ROM.
In order to use the extra RAM or ROM machines and peripherals use some MMU (like) logic and technic:
- /ROMCS combined with an MMU on the peripheral onboard (e.g. Interface I/II, Disk interfaces, etc)
- built in MMU logic (e.g. 128K, +2, Timex machines)
The MMU unit determines which physical memory (ROM or RAM) address ranges (pages) reachable on which address range of the CPU (banks).
The alignement and the size of pages and banks is fixed and usually 16KB. e.g.
- bank0 is 0x0000 to 0x3fff
- bank1 is 0x4000 to 0x7fff
- bank2 is 0x8000 to 0xbfff
- bank3 is 0xc000 to 0xffff
in the CPU address space and
- page0 is 0x00000 to 0x03fff
- page1 is 0x04000 to 0x07fff
- page7 is 0x1c000 to 0x1ffff
in the RAM (virtual address space).
Both method (ROMCS or builtin MMU) use some simple event to change the actual paging of ROM or RAM:
- pull up a pad on the edge connector
- out a byte to a specific port (e.g. 0x7ffd)
- PC register of Z80 CPU hit a specific address
- user press a (red) button which trigger an NMI
ROMCS is ROM Chip Select
The pin (really a pad) 25 on solder side of edge connector is /ROMCS. This pin connected directly to the /CS pin of ROM. Peripherals easily "switch off" the main ROM with this pad, because the ULA /ROMCS output connected here via a 680 Ohm resistor.
There are two limitation of this method:
- only the ROM address space (0x0000 - 0x3fff) is usable
- there is no /ROMCS or edge connector in plus2a/b, plus3, pentagon, etc machines
MMU is Memory Management Unit.
ZX Spectrum 16/48
The ZX Spectrum 16/48 has a very symple MMU. We can say, this is only a memory management logic.
The memory address space is divided for two part:
- lower (0x0000 - 0x7fff) where A15 (address line 15th bit) is 0
- higher (0x8000 - 0cffff) where A15 is 1
The lower address space managed by the ULA, the higher one managed by discrete logic ICs.
The management is quite simple:
- if /ROMCS is "floating" (or nothing to connected) the 16K ROM is mapped in the 0x0000 - 0x3fff range
- if the /ROMCS pin connected to logical 1 (+5V) then the ROM mapped out
- the lower 16K RAM is mapped to the 0x4000 - 0x7fff range
- if ULA read from the range 0x4000 - 0x7fff and the CPU want to reach this address range parallel, then ULA halt the CPU clock (see contended memory)
- the higher 32K RAM is mapped to the 0x8000 - 0xffff range
ZX Spectrum 128K
The MMU of ZX Spectrum 128K built up for several part:
- a HAL10H8 IC (PAL10H8) - generating the main signals of memory paging
- a 74LS174 IC (hex D flip-flop) as bank register - hold the page number of "mapped in" ROM and RAM page
- a ZX8401 IC (Mullard ULA - decoder/multiplexer) - generates addressing for RAM
- ULA - generates addressing for "contended" (video) RAM pages, when ULA read this area for build up video signal and inhibit the CPU clock if it want to access "contended" RAM pages at the same time
The 32KB ROM (23256 a 128K bit mask programmable ROM) is divided into two 16KB part:
- ROM0 - the "128K ROM"
- ROM1 - the "48K ROM"
The B4 bit of bank register directly select which ROM page mapped in 0x0000 - 0x3fff address range
The 128KB RAM is organized in two group (2x8 4164 RAM) ICs:
- upper "uncontended" RAM and
- lower "contended" RAM
Both names came from the ZX Spectrum 128 Service Manual are quite confusing:
- upper RAM contains "lower" RAM pages (0-3)
- page2 always mapped into 0x8000 - 0xbfff address range
- page0 to page3 can be mapped into 0xc000 - 0xffff address range
- lower RAM contains "upper" RAM pages (4-7)
- page5 always mapped into 0x4000 - 0x3fff address range
- page4 to page7 can be mapped into 0xc000 - 0xffff address range
B0 to B2 bits of bank register select the currently mapped in RAM page (page0 to page7) into 0xc000 - 0xffff address range.
B3 bit of bank register selects the current video RAM page, where ULA build the TV picture. B3 connected to VB (video bank) input of ULA.
- page5 of RAM (original video bank)
- page7 of RAM