Various spectrum models and peripherals use memory paging (or memory mapping) technic to extend the 64kb memory limit of Z80 CPU.
The Z80 CPU has 16 address lines and no builtin MMU unit, so it can address maximum 64KB (216) memory (or I/O) space (0x0000 - 0xffff). To use more than 64KB memory we need some technic - called "bank switching", "memory mapping", "memory paging", etc. Nowadays the term "memory paging" mostly used for memory <-> disk swapping. The MMU logic disable or enable memory chips with CS or OE (chip select, or output enable) pins and/or generate "extra" address signals for memory chips to select "memory areas".
In this description we use the term "bankN" for CPU address space ranges. The banks counted from 0 and grows from lower to higher address (e.g. CPU address space 0x0000 - 0x3fff is bank0). We use the term RAM/ROM "pageN" for memory areas. The numbering is the same as the numbering of the banks. The virtual address space of memory can spread over multiple memory IC, regardless of the fact that each data bit of an address may sit in separate RAM ICs.
The original ZX Spectrum 16K/48K (or the ZX Spectrum+) only uses maximum 64KB memory (16KB ROM and 16KB or 48KB RAM), but other models (128K) and several peripheral have extra RAM or ROM.
In order to use the extra RAM or ROM machines and peripherals use some MMU (like) logic and technic:
- /ROMCS combined with an MMU on the peripheral onboard (e.g. Interface I/II, Disk interfaces, etc)
- built in MMU logic (e.g. 128K, +2, Timex machines)
The MMU unit determines which physical memory (ROM or RAM) address ranges (pages) reachable on which address range of the CPU (banks).
The alignement and the size of pages and banks is fixed and usually 16KB. e.g.
- bank0 is 0x0000 to 0x3fff
- bank1 is 0x4000 to 0x7fff
- bank2 is 0x8000 to 0xbfff
- bank3 is 0xc000 to 0xffff
in the CPU address space and
- page0 is 0x00000 to 0x03fff
- page1 is 0x04000 to 0x07fff
- page7 is 0x1c000 to 0x1ffff
in the RAM (virtual address space).
Both method (ROMCS or builtin MMU) use some simple event to change the actual paging of ROM or RAM:
- pull up a pad on the edge connector
- out a byte to a specific port (e.g. 0x7ffd)
- PC register of Z80 CPU hit a specific address
- user press a (red) button which trigger an NMI
ROMCS is ROM Chip Select
The pin (really a pad) 25 on solder side of edge connector is /ROMCS. This pin connected directly to the /CS pin of ROM. Peripherals easily "switch off" the main ROM with this pad, because the ULA /ROMCS output connected here via a 680 Ohm resistor.
There are two limitation of this method:
- only the ROM address space (0x0000 - 0x3fff) is usable
- there is no /ROMCS on edge connector in plus2a/b, plus3, pentagon, etc machines
The management is quite simple:
- if /ROMCS is "floating" (or nothing to connected) the 16K ROM is mapped in the 0x0000 - 0x3fff range
- if the /ROMCS pin connected to logical 1 (+5V) then the ROM mapped out
MMU is Memory Management Unit.
ZX Spectrum 16/48
The ZX Spectrum 16/48 has a very symple MMU. We can say, this is only a memory management logic.
The memory address space is divided for two part:
- lower (0x0000 - 0x7fff) where A15 (address line 15th bit) is 0
- higher (0x8000 - 0cffff) where A15 is 1
The lower address space managed by the ULA, the higher one managed by discrete logic ICs.
The management is quite simple:
- the lower 16K RAM is mapped to the 0x4000 - 0x7fff range
- if ULA read from the range 0x4000 - 0x7fff and the CPU want to reach this address range parallel, then ULA halt the CPU clock (see contended memory)
- the higher 32K RAM is mapped to the 0x8000 - 0xffff range
ZX Spectrum 128K
The original "Toastrack" 128K and "Grey" +2.
The MMU of ZX Spectrum 128K built up for several part:
- a HAL10H8 IC (PAL10H8) - generating the main signals of memory paging
- a 74LS174 IC (hex D flip-flop) as bank register - hold the page number of "mapped in" ROM and RAM page and the current video RAM page
- a ZX8401 IC (Mullard ULA - decoder/multiplexer) - generates addressing for RAM
- ULA - generates addressing for "contended" (video) RAM pages, when ULA read this area for build up video signal and inhibit the CPU clock if it want to access "contended" RAM pages at the same time
The 32KB ROM (23256 a 128K bit mask programmable ROM) is divided into two 16KB part:
- ROM0 - the "128K ROM"
- ROM1 - the "48K ROM"
The B4 bit of bank register directly select which ROM page mapped in 0x0000 - 0x3fff address range
The 128KB RAM is organized in two group (2x8 4164 RAM) ICs:
- upper "uncontended" RAM and
- lower "contended" RAM
Both names came from the ZX Spectrum 128 Service Manual are quite confusing:
- upper RAM contains "lower" RAM pages (0-3)
- page2 always mapped into 0x8000 - 0xbfff address range
- page0 to page3 can be mapped into 0xc000 - 0xffff address range
- page1 and page3 are contended
- lower RAM contains "upper" RAM pages (4-7)
- page5 always mapped into 0x4000 - 0x3fff address range
- page4 to page7 can be mapped into 0xc000 - 0xffff address range
- page5 and page7 are contended
Bank register: The 74LS174 IC CLK input drived by the HAL10H8 IC bank output, which decoded from A15 and A1 and IOREQ lines. So a read or write from/to I/O port 0x7ffd (or exactly 0xxx xxxx xxxx xx0x) trigger the bank register CLK input.
The six D flip-flop (FF1 to FF6) provide the six bit of bank register (B0 to B5 respectively).
Data bus D0 to D5 connected to the 74LS174 IC D1 to D6 data inputs respectively.
The 74LS174 IC Q1 to Q3 outputs connected to the B0 to B2 inputs of HAL10H8 IC respectively. The Q4 output connected to the VB input of ULA. The Q5 output connected to the A14 input of ROM.
The Q6 output connected to the CLK input of 74LS174 via a diode. The CLK driven via a 470 ohm resistor, so if Q6 become high (1) the CLK line fixed at high level (1) and the bank register cannot writen until a reset.
The CLEAR input connected to the RESET line, so at reset the bank register cleared.
B0 to B2 bits of bank register select the currently mapped in RAM page (page0 to page7) into 0xc000 - 0xffff address range.
B3 bit of bank register selects the current video RAM page, where ULA build the TV picture. B3 connected to VB (video bank) input of ULA.
- page5 of RAM (original video bank)
- page7 of RAM
B4 bit of bank register selects the current ROM. B4 directly connected to A14 pin of the 32KB ROM IC, so:
- 0 selects the "lower" 16K - "128K ROM"
- 1 selects the "upper" 16K - "48K ROM"
B5 bit of bank register disables further changes of register until a reset.
ZX Spectrum +2A/2B, +3/3B
The 64KB ROM 2x(23256 a 128K bit mask programmable ROM) is divided into four 16KB part:
- ROM0 - the "128K ROM-1"
- ROM1 - the "128K ROM-2"
- ROM2 - the "+3DOS ROM"
- ROM3 - the "48K ROM"
The 128KB RAM is organized in two group (2x2 4464 RAM) ICs:
- uncontended RAM (page0 to page3) and
- contended RAM (page4 to page7)
- the 128K bank register on port 0x7ffd (or exactly 01xx xxxx xxxx xx0x)
- and a second bank register on port 0x1ffd (or exactly 0001 xxxx xxxx xx0x) which control the extra ROM and "special" RAM mapping functionality
This second register used for trigger the printer and the disk motor (B4 and B3) and only the low 3 bit (B0 to B2) related to memory bank switching.
Bank register +3 (on port 0x1ffd):
- B0 select "special" paging mode. In special paging mode RAM pages mapped to all banks in variouse configurations. This mode introduced, because CP/M cannot operate if ROM mapped at bank0 (0x0000-0x3fff).
- B2 the "high" bit of selected ROM page number if B0 = 0 (not "special" paging mode)
- B1 - B2 select "special" memory page configuration if B0 = 1 ("special" paging mode)
- 0b00 - RAM page0, page1, page2 and page3 mapped to bank0, bank1, bank2, bank3 respectively
- 0b01 - RAM page4, page5, page6 and page7 mapped
- 0b10 - RAM page4, page5, page6 and page3 mapped
- 0b11 - RAM page4, page7, page6 and page3 mapped
The funkcionality of the "original" 128K bank register is the same as in ZX Spectrum 128K.
Other modells, clones
Bank switching from the user perspective
|Normal mapping (128K)||Special mapping
aaa = 0 - 7
|RAM page3||RAM page7||RAM page3||RAM page3|
|RAM page2||RAM page2||RAM page6||RAM page6||RAM page6|
|RAM page5||RAM page1||RAM page5||RAM page5||RAM page7|
Rr = 0 - 3
|RAM page0||RAM page4||RAM page4||RAM page4|
Video memory (ULA)
ULA build the actual picture from RAM page5+2*V, where V = 0 or 1 in page register 0x7ffd (128K) B3 (xxxx Vxxx), regardless of actual RAM page configuration.