707
edits
Z80: Difference between revisions
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→Contended memory: Fix 128K paged address range
(→Contended memory: Try to explain things better.) |
(→Contended memory: Fix 128K paged address range) |
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Computers using the Z80 tended to run at a relatively high clock speed by for the time, compared to certain other processors such as the MOS 6502 and Motorola 6809. Doing so was required to achieve a decent level of performance, as on average, the Z80 required a larger number of clock cycles per instruction executed. This high clock speed would typically eliminate cycle stealing as a means of sharing video memory between the display generation hardware and the CPU, as the DRAM required to support this would need to be clocked at an even higher frequency. If a display is to be generated whilst video memory is being accessed, this leaves a choice of comparatively expensive VRAM with a dedicated read port for display generation, or a memory contention scheme where by the CPU will is halted when the display hardware requires access to video memory. | Computers using the Z80 tended to run at a relatively high clock speed by for the time, compared to certain other processors such as the MOS 6502 and Motorola 6809. Doing so was required to achieve a decent level of performance, as on average, the Z80 required a larger number of clock cycles per instruction executed. This high clock speed would typically eliminate cycle stealing as a means of sharing video memory between the display generation hardware and the CPU, as the DRAM required to support this would need to be clocked at an even higher frequency. If a display is to be generated whilst video memory is being accessed, this leaves a choice of comparatively expensive VRAM with a dedicated read port for display generation, or a memory contention scheme where by the CPU will is halted when the display hardware requires access to video memory. | ||
The ZX Spectrum uses a memory contention scheme, but with a slight quirk — the /MREQ line that signifies whether the Z80 is performing memory access is not decoded by the ULA of the original Sinclair models (including the 128K), meaning that the CPU may be halted briefly to avoid contention whenever it places a value onto the address bus in the address range of contended memory (i.e. memory at 0x4000–0x7fff on the 48K Spectrum, and also the range between | The ZX Spectrum uses a memory contention scheme, but with a slight quirk — the /MREQ line that signifies whether the Z80 is performing memory access is not decoded by the ULA of the original Sinclair models (including the 128K), meaning that the CPU may be halted briefly to avoid contention whenever it places a value onto the address bus in the address range of contended memory (i.e. memory at 0x4000–0x7fff on the 48K Spectrum, and also the range between 0xc000–0xffff on a 128K when contended memory is paged in). As /MREQ is not decoded, this contention applies even when the Z80 is not accessing memory, i.e. when accessing I/O ports, when performing DRAM refresh, and when certain instructions place spurious values on the address bus for no specific purpose. This issue was later fixed by Amstrad for the Spectrum +3 and +2A/+2B, but by this time, a certain amount of software had grown to depend on the behaviour of the original Sinclair models. | ||
== Bits 3 and 5 of the F register == | == Bits 3 and 5 of the F register == | ||