651
edits
Floating bus: Difference between revisions
Jump to navigation
Jump to search
m
no edit summary
m (Typographical changes) |
mNo edit summary |
||
| Line 46: | Line 46: | ||
Note that these timings will all be one T-state later on "[[Contended memory#Timing differences|late timing]]" machines. | Note that these timings will all be one T-state later on "[[Contended memory#Timing differences|late timing]]" machines. | ||
These [http://homepage.ntlworld.com/mark.woodmass/Float48k.tap 48K] and [http://homepage.ntlworld.com/mark.woodmass/Float128k.tap 128K] test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt. | These [https://web.archive.org/web/20130511213014/http://homepage.ntlworld.com/mark.woodmass/Float48k.tap 48K] and [https://web.archive.org/web/20130511212958/http://homepage.ntlworld.com/mark.woodmass/Float128k.tap 128K] test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt. | ||
The same effect is likely to be seen when reading unattached memory, such as reading the upper 32K on a 16K machine. | The same effect is likely to be seen when reading unattached memory, such as reading the upper 32K on a 16K machine. | ||