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Floating bus: Difference between revisions
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Add to hardware category, use wikitable class, tstate -> T-state
(Created page with "When the Z80 reads from an unattached port it will read the data present on the ULA bus, which will be a display byte being transferred to the video circuits or 0xFF when idle, s...") |
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Each scanline of video memory fetches breaks down into a 16 x 8 cycle sequence with two sets of display and attribute bytes (order: bitmap, attribute, bitmap+1, attribute+1) being fetched during the first 4 cycles followed by 4 idle cycles. The ULA bus remains idle for the remainder of each scanline and returns 0xFF. | Each scanline of video memory fetches breaks down into a 16 x 8 cycle sequence with two sets of display and attribute bytes (order: bitmap, attribute, bitmap+1, attribute+1) being fetched during the first 4 cycles followed by 4 idle cycles. The ULA bus remains idle for the remainder of each scanline and returns 0xFF. | ||
The following table shows the fetch cycles for the first 8 cycle sequence of the 48K and 128K models<ref>This document labels the first | The following table shows the fetch cycles for the first 8 cycle sequence of the 48K and 128K models<ref>This document labels the first T-state which ''begins'' with /INT low as T-state 0; some other resources label this as T-state 1 which will mean all T-state counts are one greater.</ref>: | ||
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Note that these timings will all be one | Note that these timings will all be one T-state later on "[[Contended memory#Timing differences|late timing]]" machines. | ||
These [http://homepage.ntlworld.com/mark.woodmass/Float48k.tap 48K] and [http://homepage.ntlworld.com/mark.woodmass/Float128k.tap 128K] test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt. | These [http://homepage.ntlworld.com/mark.woodmass/Float48k.tap 48K] and [http://homepage.ntlworld.com/mark.woodmass/Float128k.tap 128K] test programs may be used for testing an emulator's floating bus implementation. Note that the Z80 samples the data bus during the final T-state of the I/O machine cycle. All timings are relative to the ULA asserting the INTREQ line; as the Z80 samples this line during the final T-state of opcode execution, there is a minimum of a one cycle delay before the Z80 acknowledges the interrupt. | ||
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{{CC-BY-SA-techwiki|Floating bus|Floating_bus}} | {{CC-BY-SA-techwiki|Floating bus|Floating_bus}} | ||
[[Category:Hardware]] | |||