Z80: Difference between revisions

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Z80 (view source)

Revision as of 11:56, 8 April 2014

17 bytes removed ,  8 April 2014
Rearrange SCF/CCF section
(Rearrenge CMOS vs NMOS differences and BIT n,(hl) section)
(Rearrange SCF/CCF section)
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== Bits 3 and 5 of the F register ==
== Bits 3 and 5 of the F register ==
=== BIT n,(HL) ===


Upon executing BIT n,(HL) instructions, bits 3 and 5 of the F register are [http://zx.pk.ru/attachment.php?attachmentid=2989 memptr_eng.txt copied from an internally buffered register pair] now commonly referred to as MEMPTR.
Upon executing BIT n,(HL) instructions, bits 3 and 5 of the F register are [http://zx.pk.ru/attachment.php?attachmentid=2989 memptr_eng.txt copied from an internally buffered register pair] now commonly referred to as MEMPTR.


Woody has confirmed that bits 3 and 5 of the flags are copied on all BIT instructions on both a Zilog Z80 and an NEC clone (stated on the link above as being "unverified").
Woody has confirmed that bits 3 and 5 of the flags are copied on all BIT instructions on both a Zilog Z80 and an NEC clone (stated on the link above as being "unverified").
=== SCF/CCF ===
Stuart Brady discovered that how bits 3 and 5 of the flags are set after the SCF and CCF instructions actually depends on the variant of Z80 in use. On a Zilog Z80, bits 3 and 5 of the flags were set by ORing their previous values with that of A. On an NEC clone, bit 3 was unaffected, while bit 5 appears to be set by ANDing the previous value with something unknown. Previously, Ian Greenway tested this and found that bits 3 and 5 seemed simply to be copied from A, although it is not known which CPU these tests were run on. For more details, see [http://sourceforge.net/mailarchive/forum.php?thread_name=20040217082529.GH17981%40philos.lan.philosys.de&forum_name=fuse-emulator-devel here], [http://sourceforge.net/mailarchive/forum.php?thread_name=20070522223156.GA12009%40miranda.arrow&forum_name=fuse-emulator-devel here] and a more recent investigation [http://groups.google.co.uk/group/comp.sys.sinclair/msg/56dd1fd4ccb5fb3b here].
Patrik Rak however later [http://www.worldofspectrum.org/forums/showthread.php?p=669314 discovered] that the way how the flags 5 and 3 are affected after SCF/CCF actually depends on the previous instruction completed. In case of genuine Zilog CPU, if an instruction modifies the flags, the immediately following SCF/CCF does move of bits 5 and 3 from A to F, whereas if an instruction doesn't modify the flags (and after interrupt), the SCF/CCF does OR of bits 5 and 3 from A to F. In case of NEC and other clones, it is similar, except that instead of OR it does AND with some unknown value, making the result unreliable.


== Differences between NMOS and CMOS Z80s ==
== Differences between NMOS and CMOS Z80s ==
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The NMOS Z80s suffer a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction.  This behaviour, along with workarounds for this for use in interrupt handlers are documented in the [http://z80.info/zip/ZilogProductSpecsDatabook129-143.pdf Z80 Family Questions and Answers] section of the Zilog Product Specifications Databook, and is useful for detecting the model of Z80 in use, so as to determine whether the CPU (assuming it is a genuine NMOS or CMOS Z80) provides an 'OUT (C),0' instruction (NMOS), or 'OUT (C),255' instead (CMOS).
The NMOS Z80s suffer a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction.  This behaviour, along with workarounds for this for use in interrupt handlers are documented in the [http://z80.info/zip/ZilogProductSpecsDatabook129-143.pdf Z80 Family Questions and Answers] section of the Zilog Product Specifications Databook, and is useful for detecting the model of Z80 in use, so as to determine whether the CPU (assuming it is a genuine NMOS or CMOS Z80) provides an 'OUT (C),0' instruction (NMOS), or 'OUT (C),255' instead (CMOS).
=== Bits 3 and 5 of the F register after SCF/CCF ===
Stuart Brady discovered that how bits 3 and 5 of the flags are set after the SCF and CCF instructions actually depends on the variant of Z80 in use. On a Zilog Z80, bits 3 and 5 of the flags were set by ORing their previous values with that of A. On an NEC clone, bit 3 was unaffected, while bit 5 appears to be set by ANDing the previous value with something unknown. Previously, Ian Greenway tested this and found that bits 3 and 5 seemed simply to be copied from A, although it is not known which CPU these tests were run on. For more details, see [http://sourceforge.net/mailarchive/forum.php?thread_name=20040217082529.GH17981%40philos.lan.philosys.de&forum_name=fuse-emulator-devel here], [http://sourceforge.net/mailarchive/forum.php?thread_name=20070522223156.GA12009%40miranda.arrow&forum_name=fuse-emulator-devel here] and a more recent investigation [http://groups.google.co.uk/group/comp.sys.sinclair/msg/56dd1fd4ccb5fb3b here].
Patrik Rak however later [http://www.worldofspectrum.org/forums/showthread.php?p=669314 discovered] that the way how the flags 5 and 3 are affected after SCF/CCF actually depends on the previous instruction completed. In case of genuine Zilog CPU, if an instruction modifies the flags, the immediately following SCF/CCF does move of bits 5 and 3 from A to F, whereas if an instruction doesn't modify the flags (and after interrupt), the SCF/CCF does OR of bits 5 and 3 from A to F. In case of NEC and other clones, it is similar, except that instead of OR it does AND with some unknown value, making the result unreliable.


=== OUT (C),0 / OUT (C),255 instruction ===
=== OUT (C),0 / OUT (C),255 instruction ===
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