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edits
Z80: Difference between revisions
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→LD A,I and LD A,R in NMOS Z80s: Usefulness for OUT (C),0/255
(Add notable uses, compatibility with 8080, compatible CPUS and rearrange sections) |
(→LD A,I and LD A,R in NMOS Z80s: Usefulness for OUT (C),0/255) |
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== LD A,I and LD A,R in NMOS Z80s == | == LD A,I and LD A,R in NMOS Z80s == | ||
The NMOS Z80s suffer a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. This behaviour, along with workarounds for this for use in interrupt handlers are documented in the [http://z80.info/zip/ZilogProductSpecsDatabook129-143.pdf Z80 Family Questions and Answers] section of the Zilog Product Specifications Databook. | The NMOS Z80s suffer a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. This behaviour, along with workarounds for this for use in interrupt handlers are documented in the [http://z80.info/zip/ZilogProductSpecsDatabook129-143.pdf Z80 Family Questions and Answers] section of the Zilog Product Specifications Databook, and is useful for detecting the model of Z80 in use, so as to determine whether the CPU (assuming it is a genuine NMOS or CMOS Z80) provides an 'OUT (C),0' instruction (NMOS), or 'OUT (C),255' instead (CMOS). | ||
== Bits 3 and 5 of the F Register == | == Bits 3 and 5 of the F Register == | ||