Z80: Difference between revisions

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91 bytes added ,  3 April 2014
(Add a short contended memory section)
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{{Main|Contended memory}}
{{Main|Contended memory}}


Computers using the Z80 tended to run at a relatively high clock speed by for the time, compared to certain other processors such as the MOS 6502 and Motorola 6809.  Doing so was required to achieve a decent level of performance, as on average, the Z80 required a larger number of clock cycles per instruction executed.  This high clock speed would typically eliminate cycle stealing as a means of sharing video memory between the display generation hardware and the CPU.  If a display is to be generated whilst video memory is being accessed, this leaves a choice of comparatively expensive VRAM with a dedicated read port for display generation, or a memory contention scheme where by the CPU will is halted when the display hardware requires access to video memory.  The ZX Spectrum uses a memory contention scheme, but with a slight quirk — the /MREQ line that signifies whether the Z80 is performing memory access is not decoded by the original Sinclair models, meaning that the CPU can be slowed down as a result of values placed onto its address bus when not performing a memory access.  This issue was later fixed by Amstrad for the Spectrum +3 and +2A/+2B, but by this time, a certain amount of software had grown to depend on the behaviour of the original Sinclair models.
Computers using the Z80 tended to run at a relatively high clock speed by for the time, compared to certain other processors such as the MOS 6502 and Motorola 6809.  Doing so was required to achieve a decent level of performance, as on average, the Z80 required a larger number of clock cycles per instruction executed.  This high clock speed would typically eliminate cycle stealing as a means of sharing video memory between the display generation hardware and the CPU, as the DRAM required to support this would need to be clocked at an even higher frequency.  If a display is to be generated whilst video memory is being accessed, this leaves a choice of comparatively expensive VRAM with a dedicated read port for display generation, or a memory contention scheme where by the CPU will is halted when the display hardware requires access to video memory.  The ZX Spectrum uses a memory contention scheme, but with a slight quirk — the /MREQ line that signifies whether the Z80 is performing memory access is not decoded by the original Sinclair models, meaning that the CPU can be slowed down as a result of values placed onto its address bus when not performing a memory access.  This issue was later fixed by Amstrad for the Spectrum +3 and +2A/+2B, but by this time, a certain amount of software had grown to depend on the behaviour of the original Sinclair models.


== OUT (C),0 / OUT (C),255 Instruction ==
== OUT (C),0 / OUT (C),255 Instruction ==

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