ZXI standard

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ZXI logo
ZXI outline logo

The ZXI (ZX Interface) is for devices that are attached to the Spectrum edge connector. ZXI compliant devices are inter-operable with each other without conflicts. Certified devices may display the logo on their case, in their manuals, and on-screen.


The Z80 provides 16-bit I/O decoding, so in theory the Spectrum has 65536 ports available for hardware devices. In practice the Spectrum does not fully decode the I/O and there are no spare I/O ports available that do not clash with at least one existing peripheral. For example, the ULA alone uses 32768 ports (every even port). It is worth noting that the Timex clones do fully decode the I/O ports.

During the development of the ULAplus replacement ULA, a comprehensive search was carried out to determine a 16-bit port range that clashed with the least devices. An 8-bit port was located that clashed with a single device, the ZX Printer, and a hardware fix created to prevent the ZX Printer using that address. The following modification to the ZX Printer circuit prevents it being triggered by access to port xx3B.


Meanwhile, during the development of the Spectranet ethernet card, a solution was devised to enable multiple devices to page in their own ROMs using 'ripple priority'. The ZXI standard combines these two approaches into a single standard. Legacy devices that do not use ROM paging may also be certified as ZXI compliant on a case by case basis.

Port Allocation

Port allocations are currently in flux - be advised that assignments may change in the future

To have your device certified as ZXI compliant, you must apply for the required number of I/O ports in the range #hh3B. This can be done by sending a message via https://www.facebook.com/cheverongroup/.

Allocations as of 05 September 2012 It is proposed that the 256 ZXI ports (#xx3B) be divided into two areas based on the state of the A15 line.

A plug-in ULA replacement (such as a ULAPlus implementation) fitted in place of the original ULA can only access the A14 and A15 lines of the high address byte. This means that only partial decoding is possible and the device will respond to 128 of the available 256 ports.

A complete clone (i.e. not a plug-in ULA replacement) however can be given access to the full address bus and hence should decode the high bytes fully. It is proposed that any ports needed for internal functions in a clone (for example changing clock speed) be allocated from the higher 128 ports (i.e. A15 high).

Current ZXI port assignments with A15 high:

#FF   : ULAplus data
#FE   : ZX Prism Palette Control
#FD   : ZX-UNO
#FC   : ZX-UNO
#FB   : ZXID system
#EF-FB: Unassigned
#EE   : ZX Prism (?)
#E0-ED: Unassigned
#DF   : Spectrastick Data
#DE   : ZX Prism (?)
#D0-DD: Unassigned
#CF   : Spectrastick Control
#CE   : ZX Prism (?)
#C0-CD: Unassigned
#BF   : ULAplus register
#BE   : ZX Prism Palette Control
#AF-BD: Unassigned
#AE   : ZX Prism (?)
#9F-AD: Unassigned
#9E   : ZX Prism (?)
#8F-9D: Unassigned
#8E   : ZX Prism (?)
#80-8D: Unassigned

Current ZXI port assignments with A15 low:

#70-7F: MB03+ and eLeMeNt ZX
#6E-6F: SAA1099 Sound card (MB03+ and eLeMeNt ZX)
#6D   : SID R/W SID Control Register (MB03+ and eLeMeNt ZX)
#6C   : Select SID Control Register (MB03+ and eLeMeNt ZX)
#40-6B: Unassigned
#31-3F: Unassigned
#30   : NEXT (Unofficially allocated)
#26-2F: Unassigned
#24-25: NEXT (Unofficially allocated)
#20-23: Unassigned
#16-1F: Unassigned 
#10-15: NEXT (Unofficially allocated)
#04-0F: Unassigned
#03   : Spectranet page A memory select 
#02   : Spectranet page B memory select
#01   : Spectranet programmable trap register
#00   : Spectranet control register

Devices with the same function, for example IDE interfaces, may be allocated the same ports on the basis that only one of these devices should be connected at a time.

Port Decoding

ZXI compliant devices must perform complete bus decoding and take into account the M1 signal and the RFSH signal.

NMI Handling

The device must only respond to its own NMI. This is particularly important if the machine is using a ROM with a working NMI handler routine.

INT Triggering

It is possible on machines which have a straight connection from the INT signal at the rear bus, to the INT pin at the Z80 for an external devices to trigger an INT. It can block the normal ULA interrupt and inject its own INT pulses. ZXI compliant devices that use the INT signal should put a 0xFF on the data bus during the INTA cycle if the device does not use vector interrupts.


More detail required.

Legacy Device Certification

Legacy devices that do not use their own ROMs may also be certified as compliant on a case by case basis. For example, an AY expansion for the 48K machine that uses the same ports as the 128K machine, or an IF2 compatible Sinclair Joystick interface would both be certified compliant.

Certified Devices

Article license information

This article uses material from the "ZXI_interface_standard" article on the ZX Spectrum technical information wiki at Fandom (formerly Wikia) and is released under the Creative Commons Attribution-Share Alike License.